Course Duration

4 Days

Overview

In the next 5 years we can anticipate more wireless and digital communication standards, pervasive computing and widespread availability of data on the move. Therefore the growing requirements for processing speeds of the order of 10-100 billions of operations per second, the need for rapid prototyping and software definable architectures will further penetrate FPGAs into the DSP communication market.

The DSP for FPGAs course will review DSP fundamentals from the perspective of implementation within the FPGA fabric. Particular emphasis will be given to highlighting the cost, with respect to both resources and performance, associated with the implementation of various DSP techniques and algorithms.

This course has been successfully presented in the USA at the University of California, Los Angeles (UCLA) twice a year since 2002 and in the UK at the Institute for System Level Integration (ISLI) each year since 2004. The course has also been presented on-site at a number of companies throughout Europe and the USA.

The course will include:

Course Aim

To present theory, algorithms, design techniques and actual practicalities of the implementation of DSP algorithms and digital communications architectures using FPGA technology.

Course Syllabus

Public Course Schedule†

*Course organised in association with SILICA Denmark

On-Site Delivery

This course is available for On-Site delivery and can be fully tailored to meet the requirements of participants.

Audience

Analogue, RF, digital, DSP or FPGA/ASIC engineers who are interested in knowing the relevant design strategies and philosophies for implementing algorithms and applications on FPGAs will find the course beneficial.

Achievable Skills

On successful completion of the course, attendees will be able to:

• Understand the current and relevant DSP applications for FPGAs
• Know when to use an FPGA or a DSP processor or both
• Understand arithmetic issues, how to implement multiplies and adds efficiently
• Appreciate impact of rounding versus truncation
• Deal with overflow and underflow scenarios
• Perform advanced arithmetic - square roots and divides
• Use design techniques for minimizing sample wordlengths
• Design and implement efficient FIR (Finite Impulse Response) filters
• Use IIR (Infinite Impulse Response) filters in DSP for FPGA applications
• Understand the importance of retiming, pipelining, and multichannel filters
• Understand the relevance and cost of special filters such as CIC (Cascade Integrate-Comb) filters
• Understand the requirements and implementation of adaptive filtering algorithms
• Implement IF modulation and demodulation techniques
• Know why and how to implement Numerically Controlled Oscillators (NCOs)
• Understand techniques for synchronisation & digital communications timing recovery
• Understand the system architecture and implementation of a direct Digital Down Converter (DDC)
• Use DSP/FPGA components to implement a QAM (Quadrature Amplitude Modulator) transceiver
• Efficiently implement multi-channel filters for 3G applications
• Use design strategies for implementation of Orthogonal Frequency Division Multiplexing (OFDM)
• Use the QR algorithm for adaptive equalisation and beamforming
• Appreciate the application of SOC design methodologies within FPGAs
• Use Embedded Processors within FPGAs to implement DSP algorithms

Pre-requisites

This course has been carefully designed to present the complex mathematical theory often associated with DSP in an intuitive and straightforward style to a wide audience of scientists, engineers, project managers and even marketing staff. The following prior experience is useful but not essential:

• Fundamentals of DSP
• Basic communication systems
• Bachelor level mathematics

Course Presentation

This is an intensive 4 day course which will educate using a comprehensive set of notes on DSP for FPGAs. Key points will be lectured upon with derivations and technical details provided in the course notes for later self study. Following each lecture, hands-on lab sessions will be run using Xilinx FPGA hardware and software.

The course format is:

• 50% Lectures
• 40% Hands-on Labs (FPGA Software and Hardware)
• 10% Demonstartion

Laboratory Sessions

The laboratory sessions will be based upon the Xilinx DSP design flows. System Generator for Matlab/ Simulink, Xilinx ISE and XPS software tools will be used to design DSP systems for the Xilinx XUP Virtex-II Pro development kit which contains a Xilinx XC2VP30 FPGA.

Course Materials

All attendees will receive electronic and printed versions of the teaching materials. A DVD containing all the simulation models used during the course will also be distributed.

The notes provided form a superset of the materials presented on the course and will allow further in depth study after the course.

Further Information

To find out further information related to this or any other Steepest Ascent course please submit an on-line enquiry here.

†Steepest Ascent Ltd. reserves the right to cancel or modify courses in this schedule at short notice and will not accept liability for any costs or losses incurred by participants or their organisations as a result of these changes or cancelations. Prices quoted here do not include VAT or any applicable taxes. Steepest Ascent Ltd. reserve the right to change prices without any prior notice.